Sparse-carrier devices and method of fabrication

ABSTRACT

A sparse-carrier device including a crystal structure ( 10 ) formed of a first material and having a crystallographic facet ( 26 ) with a width (w) and a length and quantum dots ( 30 ) formed of a second material and positioned in at least one row on the crystallographic facet ( 26 ). The at least one row of quantum dots ( 30 ) extends along the length of the crystallographic facet ( 26 ) and is at least one quantum dot ( 30 ) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet ( 26 ). The row of quantum dots ( 30 ) form a building block for circuits based on sparse or single electron devices.

FIELD OF INVENTION

[0001] The present invention pertains to devices that operate throughthe conduction of a very small number of electrical carriers and tomethods of fabricating the devices.

BACKGROUND OF THE INVENTION

[0002] A relatively recent development in material science has been theability to fabricate structures that are small on a quantum scale. Onthis small scale, 200 Å or less, the applicable physics is no longerthat of the solid state bulk nor that of the gaseous free atom, butrather that of a quantum confined intermediate. Early in the developmentthese small scale structures were formed in layers with confinement inone dimension only. The confined structures are typically composed ofthin layers produced by MBE equipment on GaAs or other activesubstrates.

[0003] As an example of a use of these thin layers, lasers have beenmade that utilize the quantum confinement layers for carrier confinementor refractive optical confinement. In quantum-mechanically confinednanostructures, the degree of freedom in the free-electron motiondecreases as N, the number of confined dimensions, goes up. This changein the electronic density of states has long been predicted to increaseefficiency and reduce temperature sensitivity in lasers, and has beendemonstrated for N=1 and N=2. The techniques for the production of verythin layers of material with reasonable electronic mobilities requirevery meticulous crystal growth and exceedingly high purity.

[0004] For the ultimate case of N=3, there is also the occurrence ofCoulomb blockade, a phenomenon that provides the basis for the operationof single-electron devices. Generally, a 3-D confined nanostructure is asmall particle of material, e.g., semiconductor material, that is smallenough to be quantum confined in three dimensions. That is, the quantumcontained particle has a diameter that is only about 200 Å or less. Thiscreates a three dimensional well with quantum confinement in alldirections.

[0005] Traditionally, attempts to fabricate 3-D confined nanostructuresrelied on e-beam lithography. More recently, STM/AFM and self-assembledquantum dots (3-D confined nanostructures) have been fabricated.However, incorporating the 3-D confined nanostructures into a usefuldevice is very difficult and has not been accomplished in amanufacturable process.

[0006] Accordingly, it would be very beneficial to be able toefficiently manufacture 3-D confined nanostructures in a useful device.

[0007] It is a purpose of the present invention to provide 3-D confinednanostructures in a useful device.

[0008] It is another purpose of the present invention to provide a newand efficient method of manufacturing 3-D confined nanostructures.

SUMMARY OF THE INVENTION

[0009] The above problems and others are at least partially solved andthe above purposes and others are realized in a sparse-carrier deviceincluding a supporting layer having a surface, a crystal structureepitaxially grown on the surface of the supporting substrate, thecrystal structure formed of a first material and having acrystallographic facet with a width and a length substantially parallelwith the supporting layer and quantum dots formed of a second materialand positioned substantially in at least one row on the crystallographicfacet. The row of quantum dots extends along the length of thecrystallographic facet and is at least one quantum dot wide and aplurality of quantum dot long, the number of rows of quantum dots beingdetermined by the width of the crystallographic facet. A row of quantumdots forms a building block for circuits based on sparse or singleelectron devices. Generally, electrical connections may be provided tothe row of quantum dots for the passage of electrical carriers or thepropagation of changes in polarization states therealong, depending uponthe operation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Referring to the drawings:

[0011]FIGS. 1 through 4 are greatly enlarged, simplified sectional viewsillustrating a preferred method of patterning a substrate for furtherprocessing;

[0012]FIG. 5 is a greatly enlarged, simplified sectional viewillustrating crystalline material selectively grown on the patternedsubstrate of FIG. 4 in accordance with the present invention;

[0013]FIG. 6 is a greatly enlarged, simplified sectional viewillustrating crystalline material selectively grown on a facet of thecrystalline material illustrated in FIG. 5 in accordance with thepresent invention;

[0014]FIG. 7 is a greatly enlarged orthogonal view of a sparse-carrierdevice in accordance with the present invention; and

[0015]FIG. 8 is a greatly enlarged orthogonal view of an alternativeembodiment of a sparse-carrier device in accordance with the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0016] Turning now to the drawings, FIGS. 1-4 illustrate several stepsin a preferred method of masking supporting layer, more specifically agallium arsenide substrate, 10 for the fabrication of sparse-carrierdevices. While the present masking method is utilized because of itsconvenience (the substrate does not have to be removed from the growthchamber throughout the operation), other masking methods known in thesemiconductor art may be utilized, if desired. It should be understoodthat gallium arsenide substrate 10 is utilized herein for purposes ofthis description but other III-V compounds and other semiconductormaterials may be utilized in other applications. Referring specificallyto FIG. 1, a simplified sectional view of gallium arsenide substrate 10having a surface 11 is illustrated. It should be understood thatsubstrate 10 might simply be a supporting structure, such as a wafer ofthe like, or it might include various layers (not shown) formed on or inthe supporting structure.

[0017] Surface 11 of gallium arsenide substrate 10 has a film 12(generally 20 angstroms or less) of a native oxide which, as is wellknow in the art, forms substantially instantaneously upon exposure toair. The native oxide is not necessary to the present invention and isonly illustrated because it is generally present and requires specialprocedures to prevent. In some applications various types of passivationmay be used, to prevent the formation of film 12, in which case suchpassivation may have to be removed before the present procedure can beperformed. It has been found that the present technique will operategenerally as described with the surface simply being clean (i.e. noforeign matter).

[0018] A mask 15 is positioned adjacent to surface 11 of substrate 10for patterning surface 11, as will be explained presently. Mask 15generally is a shadow or metal mask but, in some special applications,it can be formed in the well known manner with photolithography as in analigner or stepper (generally includes a projected image from a mask).As will become apparent presently, one of the major advantages of thepresent technique is that photolithography and the like are notnecessary for the described masking operations. In a preferredembodiment, mask 15 is a mask plate with metal lines and other features,for example, a chrome mask. In any case, mask 15 is positioned adjacentsurface 11 so as to define one or more growth areas 16 on surface 11beneath mask 15 and one or more unmasked portions 17 on surface 11 ofsubstrate 10.

[0019] Unmasked portions 17 of surface 11 are exposed to a bright lightpreferably including deep ultraviolet, represented by arrows 21 in FIG.2. The bright light may be, for example, the type typically used inaligners, steppers, or E-beam devices in the semiconductor industry. Theterm “deep ultraviolet” refers to light in the ultraviolet range,generally with a wavelength in the range of 180 to 250 nanometers. It isbelieved that exposure to other wavelengths, such as 248 nm in aspecific example, modifies the composition of the surface oxide byforming a different kind of oxide or complex oxide molecules that aremore stable than the native oxide. The exposure to light can beperformed under a lamp. However, when the light is collimated, as in analigner or stepper, sharp features can be defined in unmasked portion 17or in masked portion 16 by mask 15. In this specific example, galliumarsenide wafer 10 with layer 12 of native oxide on the surface wasprovided. Standard bright lights, both at 185 nm and at 248 nm, wereused with the wafer being exposed through a chrome coated mask for 5minutes. Oxide film 20 with a thickness less than approximately 2 nm wasproduced in the unmasked areas.

[0020] Once oxide film 20 is grown, mask 15 is removed to expose growtharea 16, as illustrated in FIG. 3. Oxide film 20 then serves as a maskfor further process operations, such as growth, etching, and so on, andcan be easily removed in situ by heating, if necessary. As an example offurther operations, substrate 10 is then introduced into a growthchamber (not shown) and heated to a temperature of approximately 580° C.to desorb any native oxide that may still be present in growth area 16.Substrate 10 with native oxide-free growth area 16 is illustrated inFIG. 4.

[0021] While retaining substrate 10 in the growth chamber, selectivegrowth of crystalline, or semiconductor, material 25 in growth area 16is performed, as illustrated in FIG. 5. With oxide film 20 in place as amask for further growth, a predetermined amount of crystalline material25 is selectively grown in area (or areas) 16. For purposes of thisdisclosure, “selective growth” or “selectively grown” is defined asgrowing only in the specific or designated area. In this specificexample, GaAs is grown using selective area epitaxy (SAE) and welldefined crystallographic facets develop while no growth occurs on oxidefilm 20. Further, since material 25 grows in a crystalline form, growthrates and shapes are crystallographic dependent, i.e. the rate and shapeof growth are dependent upon the type of material 25 being utilized.

[0022] In the specific example illustrated in FIG. 5, opening 16 isapproximately 1 micron wide and may extend lengthwise (into and out-ofthe figure) as far as desired. GaAs is grown on exposed surface 11 ofsubstrate 10 by chemical beam epitaxy using tri-isopropylgallium andarsine as the source materials. In this specific example,tri-isopropylgallium is used because it allows for lower growthtemperatures that are more compatible with the resistless oxide film 20.Other possible processes include using triethylgallium and arsine at asubstrate temperature of approximately 620° C.

[0023] By carefully controlling the amount of growth the crystallinestructure illustrated in FIG. 5 is grown with an upper facet 26 having awidth ‘w’ of approximately 60 nm in this specific embodiment, andpreferably less than 200 nm. Two other facets 27 and 28 are also grownbut, as will be explained, are not used. The limits on the width ‘w’ offacet 26 are related to the quantum dot diameter and density. The lowerlimit for ‘w’ is equal to a quantum dot diameter. In principle, only onerow of quantum dots will be formed on the facet if the width ‘w’ is lessthan the average dot-to-dot distance, d, given by d=1/(σ)^(½), where ρis the areal dot density. For example, d=100 nm if ρ=1×10¹⁰/cm². Boththe quantum dot diameter and the density are influenced by the growthconditions. It should be noted that too much material 25 (i.e.crystalline growth) results in a peak (no upper facet 26) and too littlematerial 25 results in too wide a facet 26. Further, in this specificembodiment, the crystalline structure is arranged so that upper facet 26is the (100) facet of the GaAs. It is expected that other facets and/orfacets directed other than upwardly, may be used in other applicationsand the present embodiment is utilized only for purposes of explanation.

[0024] Turning now to FIG. 6, a second crystalline material isselectively grown on facet 26 of crystal material 25. In a specificexample, InAs was selectively grown using trimethyl indium and arsine ina chemical beam epitaxy. The growth rates of InAs are different on thevarious GaAs facets and, utilizing this face, InAs grows only on the(100) facet thick enough for strain-induced islanding to occur and aquantum structure herein referred to as a quantum dot 30 is produced.Quantum dot 30 is a small particle of material, e.g., semiconductormaterial, that is small enough to be quantum confined in threedimensions. That is, quantum dot 30 has a diameter, D, that is less thanabout 200 ÅA. This creates a three dimensional well with quantumconfinement in all directions. InAs growth on facets 27 and 28 is eithertoo slow or non-existent so that no strain-induced islanding can occuron these facets. The ability to avoid InAs growth on oxide layer 20 andthe amount of InAs that nucleates on other facets (e.g. facets 27 and28) are strongly dependent on the growth conditions.

[0025] In this specific example, the temperature of the substrate waslowered to approximately 525° C. and, using trimethylindium as thesource, indium was delivered onto facet 26 together with arsine in amultiple of cycles each lasting 6-10 seconds long. The fluxes on In andAs delivered in each cycle were equivalent to that which would providethe growth of a fraction of a monolayer (ML) of InAs on an unpatternedwafer. The flux levels and the total number of cycles thus determine thetotal amounts delivered to facet 26. During the second half of eachcycle, only arsine was delivered to facet 26 to allow the surface toapproach equilibrium conditions. Alternatively, measured amounts ofindium and arsine can also be delivered continuously. In the example ofInAs quantum dots formed on GaAs, the diameter ‘D’ is typically 30 nm orless with a height of approximately 78 nm. Also, the quantum dots areformed with a density of approximately 10⁹-10¹⁰ quantum dots/cm².Deposition of additional mismatched material results in coalescence ofindividual quantum dots and formation of dislocations.

[0026] It should be understood that the formation of the quantum dots onan unlimited surface occurs in a generally random location. However, ithas been found that the quantum dot density for given growth conditionsis, to a large extent, a function of the facet width. For a given totalindium (In) flux (for example) delivered to the surface, the arealdensity of the quantum dots increases with the facet width. Thus, byadjusting the width ‘w’ of facet 26 a row of quantum dots 30approximately one quantum dot wide and a plurality of quantum dots longis produced along the length of facet 26, as illustrated in. FIG. 7. Itshould of course be understood that a row more than one quantum dotwide, or more than one row, may be desired on a facet and, while thepresent embodiment may be used to fabricate a row of quantum dotsapproximately one quantum dot wide additional quantum dots may be formedas illustrated in FIG. 8 (discussed presently).

[0027] Generally, in the example described and illustrated in FIG. 7,electrons introduced at one end of the single row of quantum dots 30will migrate or tunnel to the opposite end if the proper potentials areapplied. While electrons are the prime carrier in this example, it isexpected that structures utilizing holes as the carriers could also befabricated using the precepts described herein. Also, in someapproaches, no carriers travel down the chain, only polarization stateschange and the effect propagates along the chain. By patterning theoxide (see FIGS. 1-4) to form desired paths and structures, varioussparse-carrier devices can be fabricated.

[0028] Referring now to FIG. 8, illustrated in greatly enlargedorthogonal view is an alternative embodiment of a sparse-carrier devicein accordance with the present invention. In the embodiment of FIG. 8,portions that are similar to those previously described with regard toFIGS. 1-7 are designated with similar numbers having a prime added toindicate the different embodiment. As previously described with regardto the first embodiment, by controlling the amount of growth of thecrystalline structure illustrated in FIG. 8 allows for the formation ofan upper facet 26′ having a width ‘w’ of approximately 180 nm in thisparticular embodiment, and preferably less than 200 nm. Two other facets27′ and 28′ are also grown but, as previously explained, are not used.The limits on the width ‘w′’ of facet 26′ are related to the quantum dotdiameter, number of rows of quantum dots, and density of the individualquantum dots. The quantum dot diameter and the density and the number ofrows of quantum dots formed are influenced by the growth conditions. Itshould be noted that too much material 25′ (i.e. crystalline growth)results in a peak (no upper facet 26′) and too little material 25′results in too wide a facet 26′. Further, in this specific embodiment,the crystalline structure is arranged so that upper facet 26′ is the(100) facet of the GaAs. It is expected that other facets and/or facetsdirected other than upwardly, may be used in other applications and thepresent embodiment is utilized only for purposes of explanation.

[0029] As previously described, a second crystalline material isselectively grown on facet 26′ of crystal material 25′. In this specificexample, InAs is selectively grown using trimethyl indium and arsine ina chemical beam epitaxy. The growth rates of InAs are different on thevarious GaAs facets and, utilizing this fact, InAs grows only on the(100) facet thick enough for strain-induced islanding to occur and aquantum structure herein referred to as quantum dots 30′ is produced. Aspreviously defined, each quantum dot 30′ is a small particle ofmaterial, e.g., semiconductor material, that is small enough to bequantum confined in three dimensions. That is, each quantum dot 30′ hasa diameter, D, that is less than about 200 Å. This creates a threedimensional well with quantum confinement in all directions.

[0030] The width, ‘w′’ of facet 261 determines the number of rows ofdots 30′ that can be obtained on that facet. The formation of InAs dots30′ on the top facet 261 is a function of a number of parameters such aswidth ‘w′’ of the top facet 26′, the width of the side facets 27′ and28′ (determines the amount of indium available for migration to top),and the indium migration length. These factors are dependent upon growthtemperature, V/III ratio and the absolute growth rate.

[0031] When ‘w′’ of top facet 26′ decreases below 200 nm, the spatialdistribution of dots 30′ becomes more regular. Randomness is high whenthe growth temperature is low and the flux ratio is high.

[0032] When the indium migration lengths are increased by increasing thetemperature and decreasing the V/III ratio, a regularity in thearrangement of dots 30′ results and it begins to form rows 32 along topfacet 26′. While the change in growth conditions affects the size ofdots 30′, the ‘w′’ of top facet 26′ directly determines the number ofrows 32 possible. Thus, by controlling the growth conditions and bycontrolling ‘w′’ of top facet width 26′ (which is a function of thethickness of the epitaxial GaAs grown for a given oxide opening), therows of InAs dots 30′ on the top facet 261 and their size can becontrolled. Generally, the highest concentration of In is found on theedge and thus the first rows of quantum dots 30′ to form are located atedge 31. If space allows, this formation of quantum dots 30′ about edge31 results in a constraint of the remaining area of top facet 26′ andthus the formation of additional rows 32 of quantum dots 30′.

[0033] In addition, with the migration of indium from the sidewalls upto top facet 26′, the indium density tends to be highest at the facetedges 31. Thus dots 30′ will first form at the facet edges 31. If ‘w′’is wide enough, two aligned rows 32 of dots 30′ will form at the twoedges 31. If the top facet 26′ is formed with a width, ‘w′’ large enoughfor three rows (as illustrated), a middle row 33 of dots 30′ will appearbetween the two edge rows 32. In that the width ‘w′’ of epitaxiallygrown facet 26′ is not limited, the number of rows of quantum dots 30′is accordingly not limited. Only a single material is required forfabrication of the quantum dots 30′, thus ease in fabrication isachieved as compared to those devices which utilize multiple layers withdifferent compositions. In that etching is not used to fabricate topfacet 26′, alignment of one or more rows of quantum dots 30′ within acouple of tens of manometers is achieved.

[0034] Generally, and as previously described and illustrated withrespect to FIG. 7, electrons introduced at one end of each row ofquantum dots 30′ will migrate or tunnel to the opposite end if theproper potentials are applied. It should be understood that variouselectronic properties may be experienced as a result of the proximity ofthe rows. While electrons are the prime carrier in this example, it isexpected that structures utilizing holes as the carriers could also befabricated using the precepts described herein. Also, in someapproaches, no carriers travel down the chain, only polarization stateschange and the effect propagates along the chain. By patterning theoxide (see FIGS. 1-4) to form desired paths and structures, varioussparse-carrier devices can be fabricated.

[0035] Thus, an efficient method of manufacturing sparse-carrier devicesand a great variety of sparse electron devices have been disclosed.Further, while specific examples are utilized herein for purposes ofexplanation, those skilled in the art will understand that manyvarieties of materials and forms may be utilized.

[0036] While we have shown and described specific embodiments of thepresent invention, further modifications and improvements will occur tothose skilled in the art. We desire it to be understood, therefore, thatthis invention is not limited to the particular forms shown and weintend in the appended claims to cover all modifications that do notdepart from the spirit and scope of this invention.

What is claimed is:
 1. A sparse-carrier device comprising: a supportinglayer having a surface; a crystallographic facet of a first materialepitaxially grown on the surface of the supporting layer, thecrystallographic facet having a surface with a width and a lengthsubstantially parallel with the supporting layer; and quantum dotsformed of a second material and positioned substantially in at least onerow on the surface only of the crystallographic facet, the row extendingalong the length of the crystallographic facet and being at least onequantum dot wide and a plurality of quantum dots long, the number ofrows of quantum dots determined by the width of the crystallographicfacet.
 2. A sparse-carrier device as claimed in claim 1 wherein thewidth of the crystallographic facet is defined to restrict formation ofthe second material thereon to a one quantum dot wide row of quantumdots.
 3. A sparse-carrier device as claimed in claim 2 wherein the widthof the crystallographic facet is less than approximately 200 nm.
 4. Asparse-carrier device as claimed in claim 3 wherein the width of thecrystallographic facet is less than approximately 200 nm.
 5. Asparse-carrier device as claimed in claim 1 wherein the first materialincludes gallium arsenide.
 6. A sparse-carrier device as claimed inclaim 5 wherein the second material includes indium arsenide.
 7. Asparse-carrier device as claimed in claim 6 wherein the crystallographicfacet of the first material is a (100) facet.
 8. A sparse-carrier deviceas claimed in claim 1 wherein the quantum dots have a diameter ofapproximately 25 nm.
 9. A sparse-carrier device as claimed in claim 1including in addition a portion of the supporting layer covered by adeep ultraviolet oxide film positioned to define the size and shape ofthe crystallographic facet.
 10. A sparse-carrier device comprising: asupporting layer having a surface; a crystallographic facet includinggallium arsenide selectively grown on the surface of the supportinglayer, the crystallographic facet having an upper surface with a widthand a length substantially parallel with the supporting layer; indiumbased quantum dots formed in at least one row on the upper surface ofthe crystallographic facet, the row extending along the length of thecrystallographic facet and being at least one quantum dot wide and aplurality of quantum dots long, the number of rows of quantum dotsdetermined by the width of the crystallographic facet; thecrystallographic facet being selected so that the quantum dotsselectively form only on the upper surface of the crystallographicfacet; and the crystallographic facet being defined with a width torestrict formation of the indium based quantum dots thereon to the atleast one quantum dot wide row of quantum dots.
 11. A sparse-carrierdevice as claimed in claim 10 wherein the width of the crystallographicfacet is less than approximately 1.5 μm.
 12. A sparse-carrier device asclaimed in claim 11 wherein the width of the crystallographic facet isless than approximately 200 nm.
 13. A sparse-carrier device as claimedin claim 10 wherein the crystallographic facet is a (100) facet.
 14. Asparse-carrier device as claimed in claim 10 wherein the quantum dotshave a diameter of approximately 25 nm.
 15. A sparse-carrier device asclaimed in claim 10 including in addition a portion of the surface ofthe supporting layer covered by a deep ultraviolet oxide film positionedto define the size and shape of the crystallographic facet.
 16. A methodof fabricating a sparse-carrier device comprising the steps of:providing a crystal substrate of a first material; forming a crystalstructure on the crystal substrate, the crystal structure being formedby epitaxially growing a crystallographic facet of the first materialwith a width and a length; and selectively growing quantum dots of asecond material in at least one row on the crystallographic facet, theat least one row extending along the length of the crystallographicfacet and being at least one quantum dot wide and a plurality of quantumdots long, the number of rows of quantum dots determined by the width ofthe crystallographic facet.
 17. A method of fabricating a sparse-carrierdevice as claimed in claim 16 wherein the step of selectively growingquantum dots includes covering portions of the crystal substrate, otherthan the crystal structure, with an oxide.
 18. A method of fabricating asparse-carrier device as claimed in claim 16 wherein the step of growingthe crystallographic facet includes restricting the width of thecrystallographic facet to a width that restricts formation of the secondmaterial thereon to the one quantum dot wide row of quantum dots.
 19. Amethod of fabricating a sparse-carrier device as claimed in claim 18wherein the step of restricting the width of the crystallographic facetincludes restricting the width to less than approximately 1.5 μm.
 20. Amethod of fabricating a sparse-carrier device as claimed in claim 19wherein the step of restricting the width of the crystallographic facetincludes restricting the width to less than approximately 200 nm.
 21. Amethod of fabricating a sparse-carrier device as claimed in claim 16wherein the step of growing the crystallographic facet includes growinga (100) facet.